Reliability issues in very large scale integrated (VLSI) integrated circuits have been a growing concern, as technology trends in semiconductor technologies continues to grow and, show progressive downscaling of feature sizes, of the large scale integrated circuits. As an example, one major reliability issue of VLSI is bias temperature instability (BTI), which causes threshold voltage, Vth, of CMOS transistors of the VLSI, to increase over time, under voltage stress, resulting in a temporally-dependent degradation of digital logic circuit delay of VLSI. BTI is also a dominant reliability concern for nano-scale PFET (NBTI) and NFET (PBTI) transistors of VLSI. NBTI (Negative Bias temperature instability) occurs under negative gate voltage (e.g., Vgs=−VDD), and is measured as an increase in the magnitude of threshold voltage. This, consequently, affects P-type metal-oxide-semiconductor (PMOS) transistor, and degrades device drive current, circuit speed, noise margin, and the matching property of the integrated circuit.